1. Field of the Invention
The present invention relates to an automatic maximum theoretical yield calculating apparatus for obtaining chip layout for producing the maximum number of chips from a wafer at the time of producing chips from a wafer, automatically calculating the maximum theoretical yield of chips and also automatically calculating specifications of an exposing device to realize production of chips with the minimum number of times of exposure and a computer-readable recording medium storing programs to execute automatic calculation of maximum theoretical yield with a computer.
2. Description of the Related Art
It is very effective, in manufacture of semiconductor devices, for cost reduction of products to design the layout of chips on the wafer to obtain the maximum number of chips in view of obtaining the theoretical maximum number of chips from a sheet of wafer and obtain the so-called maximum theoretical yield through the manufacture under the design explained above. It is because the manufacturing unit price per chip or product can be lowered by increasing the number of chips per water, namely raising the yield, since wafer cost is generally not different to a large extent in the same manufacturing method in the single line.
For example, when chip layout in the area effective to manufacture i.e. the effective range of a wafer aiming at the theoretical yield of fifty-eight as shown in FIG. 27A is compared with the chip layout aiming at the theoretical yield of sixty-one as shown in FIG. 27B, the latter layout is apparently advantageous from the viewpoint of manufacturing cost.
A method of obtaining such maximum theoretical yield is disclosed, for example, in the Japanese Published Unexamined Patent Application No. Sho 63-250811 entitled as "Semiconductor Wafer".
However, in this Japanese Published Unexamined Patent Application No. Sho 63-250811, a calculation example for determining the chip layout on a wafer to obtain the maximum number of chips, namely the maximum theoretical number of chips is disclosed but it is difficult to apply this calculation result to the actual wafer manufacturing process.
It is because chip layout is determined by a semiconductor exposing device such as a stepper, and so forth in the actual wafer manufacturing process and therefore layout for assuring the maximum theoretical yield cannot be realized unless various specifications for determining the exposing layout by the semiconductor exposing device are automatically provided in the chip layout for obtaining the maximum theoretical yield.
In other words, in the wafer manufacturing process, a plurality of chips are generally grouped by a sheet of mask and these chips are exposed on the wafer under this condition with a wiring pattern printing device which is called a semiconductor exposing device. In this timing, since the semiconductor manufacturing line is required to raise productivity per a short period of time, it is a very important factor for improvement of the productivity, in the layout for obtaining the same theoretical yield, how to reduce the number of times of exposing process for the layout of chips.
For example, when the theoretical yield is sixty-one as shown in FIG. 28A and FIG. 28B, the layout shown in FIG. 28B in which the number of times of exposing process is nineteen is apparently more advantageous in the point of view of manufacturing cost than the layout shown in FIG. 28A in which the number of times of exposing process is twenty-one.
However, the method to realize the minimum number of times of exposing process assuring the maximum theoretical yield is not yet proposed.